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CS5233-3 500 mA and 1.5 A, 3.3 V Dual Input Linear Regulator with Auxiliary Control
The CS5233-3 provides a glitch-free 3.3 V output from one of three possible supplies, (VIN, VSB and 3.3 VAUX). An on-chip linear regulator powers the output when either VIN or VSB is available. Otherwise AuxDrv turns on an external PFET, which connects the 3.3 VAUX supply to the output. The CS5233-3 is intended to provide power to an ASIC on a PCI Network Interface Card (NIC), and meets Intel's "Instantly Available" power requirements which follow from the Advanced Configuration and Power Interface (ACPI) standards. Other applications include desktop computers, power supplies with multiple input sources, and PCMCIA interface cards. The CS5233-3 linear regulator provides a fixed 3.3 V output at up to 1.5 A with an overall accuracy of 2%. The internal NPN - PNP composite pass transistor provides a low dropout voltage and requires less supply current than a straight PNP design. Full protection with both current limit and thermal shutdown is provided. Designed for low reverse current, the IC prevents excessive current from flowing from VOUT to either VIN or ground when the regulator input voltage is lower than the output. The auxiliary drive control feature allows the use of an external PFET to supply power to the output when the regulator supplies are off. The CS5233-3 regulator is available in two package types: the 5 Lead D2PAK package (TO-263) and SOIC-8 with 4 Lead Fused (DF8) package. When powered from the VIN source, the D2PAK-5 is rated for 1.5 A and the SOIC-8 is rated for 500 mA. Both packages are rated for 500 mA when only powered from the VSB source.
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D2PAK-5 DP SUFFIX CASE 936AC 1 5 SOIC-8 D SUFFIX CASE 751
8 1
PIN CONNECTIONS AND MARKING DIAGRAMS
Pin 1. VSB 2. VIN 3. GND 4. VOUT 5. AuxDrv
CS5233-3 AWLYWW
1 1 5233- ALYW3 8
VSB VIN VOUT AuxDrv
GND GND GND GND
* Linear Regulator - 3.3 V 2% Output Voltage - Current Limit - Thermal Shutdown with Hysteresis - 400 mA Reverse Current - ESD Protected * System Power Management - Auxiliary Supply Control - "Glitch Free" Transition Between 3 Sources - Similar to CS5231-3 * High Output Current Capability - 1.5 A D2PAK-5 - 500 mA SOIC-8 DF8 * Internally Fused Leads in SOIC-8 Package
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device CS5233-3GDP5 CS5233-3GDPR5 CS5233-3GDF8 CS5233-3GDFR8 Package D2PAK-5 D2PAK-5 SOIC-8 SOIC-8 Shipping 50 Units/Rail 750 Tape & Reel 95 Units/Rail 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2004
1
January, 2004 - Rev. 6
Publication Order Number: CS5233-3/D
CS5233-3
+3.3 VAUX D G VSB VIN 10 mF min ESR < 1.0 W
+
S
VSB VIN GND 10 mF min ESR < 1.0 W
+
AuxDrv CS5233-3 VOUT
+
VDD ASIC
10 mF min ESR < 1.0 W
GND
Figure 1. Application Diagram, 5.0 V to 3.3 V Dual Input Regulator with Auxiliary PFET Power Switch
ABSOLUTE MAXIMUM RATINGS*
Rating Operating Junction Temperature Lead Temperature Soldering: Storage Temperature Range ESD Susceptibility (Human Body Model) 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value 150 230 peak -65 to +150 2.0 Unit C C C kV
ABSOLUTE MAXIMUM RATINGS
Pin Name IC Power Input (Main) IC Power Input (Standby) Output Voltage Auxiliary Drive Output IC Ground Pin Symbol VIN VSB VOUT AuxDrv GND VMAX 6.0 V 6.0 V 6.0 V 6.0 V N/A VMIN -0.3 V -0.3 V -0.3 V -0.3 V N/A ISOURCE 100 mA 100 mA Internally Limited 10 mA N/A ISINK Internally Limited Internally Limited 100 mA 50 mA N/A
ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 150C; 4.75 V < VIN; VSB < 6.0 V; COUT 10 mF
with ESR < 1.0 W, IOUT = 10 mA; unless otherwise specified.) Characteristic Linear Regulator Output Voltage Line Regulation Load Regulation 10 mA < IOUT < IMAX. (Note 2) IOUT = 10mA; VSOURCE = 4.75 V to 6.0 V. (Note 3) VSOURCE = 5.0 V; IOUT = 10 mA to IMAX. (Notes 2, 3) 3.234 - 2% - - 3.3 1.0 5.0 3.366 + 2% 5.0 15 V mV mV Test Conditions Min Typ Max Unit
2. IMAX = 1.5 A for D2PAK-5 only and with VIN > 4.75 V, otherwise IMAX = 500 mA. 3. Applies to either VIN or VSB.
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CS5233-3
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 150C; 4.75 V < VIN; VSB < 6.0 V; COUT 10 mF with ESR < 1.0 W, IOUT = 10 mA; unless otherwise specified.)
Characteristic Linear Regulator Ground Current IOUT = 10 mA IOUT = 500 mA IOUT = 1.5 A (Note 4) VSOURCE = 0 V; VOUT = 3.3 V (Note 4) 0 V < VOUT < 3.2 V VIN > 4.25 V 0 V < VOUT < 3.2 V; VIN < 4.25 V; VSB > 4.25 V (Note 5) (Note 5) - - - - 0.55 1.6 0.55 150 - 2.0 3.0 9.0 0.4 0.8 2.4 0.8 180 25 3.0 6.0 20 1.0 1.3 4.5 1.3 210 - mA mA mA mA A A A C C Test Conditions Min Typ Max Unit
Reverse Current Current Limit VIN Input SOIC-8 D2PAK-5 Current Limit VSB Input Either Package Thermal Shutdown Thermal Shutdown Hysteresis Auxiliary Drive VIN Turn-On Threshold VIN Turn-Off Threshold VSB Turn-On Threshold VSB Turn-Off Threshold Threshold Hysteresis AuxDrv Peak Voltage
VSB = 0 V; Ramp VIN up until AuxDrv goes high and regulator turns on VSB = 0 V; Ramp VIN down until AuxDrv goes low and regulator turns off VSB = 0 V; Ramp VSB up until AuxDrv goes high and regulator turns on VSB = 0 V; Ramp VSV down until AuxDrv goes low and regulator turns off - VOUT = 0 V; 0 V < VSOURCE < 2.0 V (Note 4) VOUT = 0 V; IAuxDrv = 100 mA; 2.0 V < VIN < 4.25 V; 2.0 V < VSB < 4.25 V VOUT = 3.0 V; IAuxDrv = 100 mA; 0 V < VIN < 4.25 V; 0 V < VSB < 4.25 V VIN or VSB > 4.65 V VAuxDrv = 1.0 V; VSOURCE = 4.0 (Note 4) Step VSOURCE from 4.0 V to 5.0 V (Notes 4, 5) Step VSOURCE from 5.0 V to 4.0 V (Notes 4, 5) VIN = 0 V and VIN > 4.7 V (Notes 4, 5)
4.35 4.25 4.35 4.25 75 - - - 3.75 0.5 - - 5.0
4.5 4.4 4.5 4.4 100 0.4 0.1 0.1 4.0 6.0 20 1.0 10
4.65 4.55 4.65 4.55 125 1.8 0.4 0.4 - 25 40 10 25
V V V V mV V V V V mA ms ms kW
AuxDrv High Voltage AuxDrv Pin Current Limit VAuxDrv Turn-Off Response Time VAuxDrv Turn-On Response Time Pull-Up Resistance
4. Applies to either VIN or VSB. 5. Guaranteed by design, not 100% production tested.
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CS5233-3
PACKAGE PIN DESCRIPTION
Package Lead # D2PAK-5 1 2 3, Tab 4 5 SOIC-8 Narrow 1 2 5, 6, 7, 8 3 4 Lead Symbol VSB VIN GND VOUT AuxDrv Standby 5.0 V input voltage. 5.0 V Main input voltage. Ground and IC substrate connection. Regulated output voltage. Control voltage for the external PFET switched auxiliary supply. This pin drives low if VIN and VSB are less than 4.4 V (typical), otherwise it is pulled up to the greater of VIN or VSB through an internal diode and 10 kW resistor. Function
VIN VIN UV Comparator + - ENABLE
VOUT
VSB VSB UV Comparator + - AuxDrv Current Limit Internal BIAS Bandgap Reference Thermal Shutdown ENABLE
Error Amplifier - + GND
Figure 2. Block Diagram
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CS5233-3
TYPICAL PERFORMANCE CHARACTERISTICS
3.310 3.5 3.0 Output Voltage (V) 3.305 VOUT (V) 2.5 2.0 1.5 1.0 0.5 3.290 0 20 40 60 80 100 Junction Temperature (C) 120 0 0 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 3.5 4.0 VSB = 5.0 V VIN = 5.0 V
3.300
3.295
Figure 3. Output Voltage vs. Junction Temperature, Output Voltage when Powered by VIN or VSB
3.5
Figure 4. Output Voltage vs. Load Current, VSB Values Taken with VIN = 0 V
Ground Current (mA)
3.0 VSB = 5.0 V 2.5 VIN = 5.0 V 2.0
Reverse Current (mA)
460
440
420 1.5 0 0.25 0.50 0.75 1.00 Load Current (A) 1.25 1.50 0 20 40 60 80 Junction Temperature (C) 100 120
Figure 5. Ground Pin Current vs. Output Current, VSB Data with VIN = 0 V
Figure 6. Reverse Current vs. Junction Temperature
VOUT
5.0 4.0
Output Current
VIN
Figure 7. Transient Load Response, Transient Response for 1.5 A Step Load, VIN = 5.0 V, COUT = 33 mF @ 0.4 W ESR
AuxDrv
Figure 8. AuxDrv Response Time
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CS5233-3
4.52 4.50 VIN Threshold Voltage (V) 4.48 4.46 4.44 4.42 4.40 4.38 0 20 VIN Turn-Off Threshold 40 60 80 100 Junction Temperature (C) 120 VIN Turn-On Threshold 4.5
AuxDrv High Voltage (V)
4.4
4.3 VIN = 4.65 V 0 20 40 60 80 100 Junction Temperature (C) 120
Figure 9. VIN Threshold vs. Junction Temperature, Typical Minimum and Maximum Threshold Voltages to Switch AuxDrv Control
Figure 10. AuxDrv High Voltage vs. Junction Temperature
4.0 AuxDrv Voltage (V)
2.0 27C 125C
0C
0 0 2.0 Input Voltage (V) 4.0 4.5
Figure 11. AuxDrv Voltage vs. Input Voltage (VSB or VIN) at Three Temperatures
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CS5233-3
APPLICATIONS INFORMATION
INPUT AND OUTPUT VOLTAGE MATRIX
D2PAK-5 0V 3.3 VAUX 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 1.5 A 3.3 VREG @ 1.5 A 3.3 VREG @ 1.5 A 3.3 VREG @ 1.5 A
VIN 0V 0V 0V 0V 5.0 V 5.0 V 5.0 V 5.0 V
VSB 0V 0V
3.3 VAUX 0V 3.3 V 0V 3.3 V 0V 3.3 V 0V 3.3 V
AuxDrv/5.0 V Detect On (low) On (low)
VOUT ,
5.0 V 5.0 V 0V 0V
Off (high) Off (high) Off (high) Off (high) Off (high) Off (high)
5.0 V 5.0 V
THEORY OF OPERATION
Linear Regulator
The CS5233-3 is a dual input fixed 3.3 V linear regulator that contains an auxiliary drive control feature. When VIN alone is present, or VIN and VSB are simultaneously present, the CS5233-3 uses the VIN supply to generate the 3.3 V output at currents of up to 1.5 A. When VSB alone is present, the CS5233-3 uses the VSB supply to generate the 3.3 V output at currents of up to 500 mA. The linear regulator is composed of a composite PNP-NPN pass transistor to provide low-voltage dropout capability. An output capacitor greater than 10 mF with equivalent series resistance (ESR) less than 1.0 W is required for compensation. More information is provided in the Stability Considerations section.
Auxiliary Drive Feature
load. The AuxDrv is low only when neither VIN nor VSB are available. There is 100 mV of hysteresis (typical) in the circuitry that determines if VIN or VSB are present. STABILITY CONSIDERATIONS The output capacitor helps determine three main characteristics of a linear regulator: loop stability, load transient response, and start-up delay. The CS5233-3 is designed to be stable with an output capacitor that has a minimum value of 10 mF and an equivalent series resistance less than 1.0 W. To guarantee loop stability, the output capacitor should be located close to the regulator output and ground pins. The load transient response, during the time it takes the regulator to respond, is also determined by the output capacitor. For large changes in load current, the ESR of the output capacitor causes an immediate drop in output voltage given by:
DV + DI ESR
The CS5233-3 provides an auxiliary drive feature that allows a load to remain powered even if both supplies to the IC are absent. An external p-channel FET is the only additional component required to implement this function when the auxiliary power supply is available. The PFET gate is connected to the IC's AuxDrv output, the PFET drain is connected to the auxiliary power supply, and the PFET source is connected to the load. The polarity of this connection is very important, since the PFET body diode will be connected between the load and the auxiliary supply. If the PFET is connected with its drain to the load and its source to the supply, the body diode could be forward-biased if the auxiliary supply is not present. This would result in the linear regulator providing current to everything on the auxiliary supply rail. The AuxDrv (5.0 V detect) output is pulled up to the input voltage through an internal resistor when VIN or VSB are available. If VIN and VSB are not available or both drop below 4.4 V, the AuxDrv output goes low, turning on an external PFET that connects the 3.3 V auxiliary supply to the
There is then an additional drop in output voltage given by:
DV + DI TC
where T is the time for the regulation loop to begin to respond, (typically 4.0 ms for the CS5233-3). If tight output regulation is required with fast changing loads, a capacitor network of tantalum and low ESR ceramic capacitors can be added as close to the load as possible, with enough capacitance and a reduced ESR to minimize the voltage change, as determined by the formulas above.
Input Capacitors and the Vin Thresholds
A capacitor placed on the VIN pin will help to improve transient response. During a load transient, the input capacitor serves as a charge "reservoir," providing the needed extra current until the external power supply can
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AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
VOUT , SOIC-8 0V 3.3 VAUX 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA 3.3 VREG @ 500 mA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Input
Outputs
AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA AAAA
CS5233-3
respond. One of the consequences of providing this current is an instantaneous voltage drop at VIN due to capacitor ESR. The magnitude of the voltage change is again the product of the current change and the capacitor ESR. It is very important to consider the maximum current step that can exist in the system. If the change in current is large enough, it is possible that the instantaneous voltage drop on VIN will exceed the VIN threshold hysteresis, and the IC will enter a mode of operation resembling an oscillation. As the part turns on, the output current IOUT will increase, reaching current limit during initial charging. Increasing IOUT results in a drop at VIN such that the shutdown threshold is reached. The part will turn off, and the load current will decrease. As IOUT decreases, VIN will rise and the part will turn on, starting the cycle all over again. This oscillatory operation is most likely at initial start-up when the output capacitance is not charged, and in cases where the ramp-up of the VIN supply is slow. It may also occur during the power transition when the linear regulator turns on and the PFET turns off. A 20 ms delay exists between turn-on of the regulator and the AuxDrv pin pulling the gate of the PFET high. This delay prevents "chatter" during the power transitions. If required, using a few capacitors in parallel to increase the bulk charge storage and reduce the ESR should give better performance than using a single input capacitor. Short, straight connections between the power supply and VIN lead along with careful layout of the PC board ground plane will reduce parasitic inductance effects. Wide VIN and VOUT traces will reduce resistive voltage drops.
Choosing the PFET Switch
The following board layout practices will help to minimize output voltage errors: * Always place the linear regulator as close to both load and output capacitors as possible. * Always use the widest possible traces to connect the linear regulator to the capacitor network and to the load. * Connect the load to ground through the widest possible traces. * Connect the IC ground to the load ground trace at the point where it connects to the load.
Current Limit
The CS5233-3 has internal current limit protection. Output current is limited to a typical value of 3.0 A for the D2PAK using VIN and 800 mA using VSB, even under output short circuit conditions. If the load current drain exceeds the current limit value, the output voltage will be pulled down and will result in an out of regulation condition.
Thermal Shutdown
The CS5233-3 has internal temperature monitoring circuitry. The output is disabled if junction temperature of the IC reaches 180C. Thermal hysteresis is typically 25C and allows the IC to recover from a thermal fault without the need for an external reset signal. The monitoring circuitry is located near the composite PNP-NPN output transistor, since this transistor is responsible for most of the on-chip power dissipation. The combination of current limit and thermal shutdown will protect the IC from nearly any fault condition.
Reverse Current Protection
The choice of the external PFET switch is based on two main considerations. First, the PFET should have a very low turn-on threshold. Choosing a switch transistor with VGS(ON) 1.0 V will ensure the PFET will be fully enhanced with only 3.3 V of gate drive voltage. Second, the switch transistor should be chosen to have a low RDS(ON) to minimize the voltage drop due to current flow in the switch. The formula for calculating the maximum allowable on-resistance is
V * VOUT(MIN) RDS(ON)MAX + AUX(MIN) 1.5 IOUT(MAX)
VAUX(MIN) is the minimum value of the auxiliary supply voltage, VOUT(MIN) is the minimum allowable output voltage, IOUT(MAX) is the maximum output current and 1.5 is a "fudge factor" to account for increases in RDS(ON) due to temperature.
Output Voltage Sensing
During normal system operation, the auxiliary drive circuitry will maintain voltage on the VOUT pin. IC reliability and system efficiency are improved by limiting the amount of reverse current that flows from VOUT to ground and from VOUT to VIN. Current flows from VOUT to ground through the feedback resistor divider that sets up the output voltage, typically 400 mA. Current flow from VOUT to VIN will be limited to leakage current after the IC shuts down. On-chip RC time constants are such that the output transistor should be turned off well before VIN drops below the VOUT voltage.
Calculating Power Dissipation and Heatsink Requirements
It is not possible to remotely sense the output voltage of the C5233-3 since the feedback path to the error amplifier is not externally available. It is important to minimize voltage drops due to metal resistance of high current PC board traces. Such voltage drops can occur in both the supply traces and the return traces.
Most linear regulators operate under conditions that result in high on-chip power dissipation. This results in high junction temperatures. Since the IC has a thermal shutdown feature, ensuring the regulator will operate correctly under normal conditions is an important design consideration. Some heatsinking will usually be required. Thermal characteristics of an IC depend on four parameters: ambient temperature (TA in C), power dissipation (PD in watts), thermal resistance from the die to
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CS5233-3
the ambient air (qJA in C per watt) and junction temperature (TJ in C). The maximum junction temperature is calculated from the formula below:
TJ(MAX) + TA(MAX) ) qJA PD(MAX)
Maximum ambient temperature and power dissipation are determined by the design, while qJA is dependent on the package manufacturer. The maximum junction temperature for operation of the CS5233-3 within specification is 150C. The maximum power dissipation of a linear regulator is given as
PD(MAX) + (VIN(MAX) * VOUT(MIN)) ILOAD(MAX) ) VIN(MAX) IGND(MAX)
by the IC leads and the tab of the D2PAK package, and since the IC leads and tab are soldered directly to the PC board. Modification of qSA is the primary means of thermal management. For surface mount components, this means modifying the amount of trace metal that connects to the IC. The thermal capacity of PC board traces is dependent on how much copper area is used, if the IC is in direct contact with the metal, whether the metal surface is coated with some type of sealant, and whether there is airflow across the PC board. The chart provided below shows heatsinking capability of a square, single sided copper PC board trace. The area is given in square millimeters, and it is assumed there is no airflow across the PC board.
70
where IGND(MAX) is the IC bias current. It is possible to change the effective value of qJA by adding a heatsink to the design. A heatsink serves in some manner to raise the effective area of the package, thus improving the flow of heat from the package into the surrounding air. Each material in the path of heat flow has its own characteristic thermal resistance, all measured in C per watt. The thermal resistances are summed to determine the total thermal resistance between the die junction and air. There are three components of interest: junction-to-case thermal resistance (qJC), case-to-heatsink thermal resistance (qCS) and heatsink-to-air thermal resistance (qSA). The resulting equation for junction-to-air thermal resistance is
qJA + qJC ) qCS ) qSA, or qJA + qJC ) qSA for qCS + 0
60 50 40 30 20 10 0
Thermal Resistance, CW
0
The value of qJC for the CS5233-3 is provided in the Packaging Information section of this data sheet. qCS can be considered zero, since heat is conducted out of the package
2000 4000 PC Board Trace Area (mm2)
6000
Figure 12. Thermal Resistance Capability of Copper PC Board Metal Traces
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CS5233-3
PACKAGE DIMENSIONS
D2PAK-5 DP SUFFIX CASE 936AC-01 ISSUE O
For D2PAK Outline and Dimensions - Contact Factory
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CS5233-3
PACKAGE DIMENSIONS
SOIC-8 DF SUFFIX CASE 751-07 ISSUE AA
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT
1.52 0.060 7.0 0.275 4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
Figure 13. SOIC-8
PACKAGE THERMAL DATA Parameter RqJC RqJA Typical Typical D2PAK-5 1.0-4.0 10-50* SOIC-8 25 110 Unit C/W C/W
*Depending on thermal properties of substrate. RqJA = RqJC + RqCA.
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CS5233-3
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CIS5233-3/D

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